The invention relates to the general field of silicon integrated circuits with particular reference to interconnection technology, particularly borderless contacts.
As component densities in integrated circuits continue to increase, ways are constantly being sought to make the most efficient use possible of all chip real estate. A particular example is the development of borderless contacts. In the prior art, it was standard to provide a border around all metal vias where they emerged at a surface. Such a border allowed a small amount of misalignment, relative to the next level of metalization to be tolerated.
FIG. 1 shows an example of a borderless contact, seen in schematic cross-section. Metal via 19 is intended to contact source (or drain) area 14 which is adjacent to insulation-filled shallow isolation trench 12. The detailed process for making the contact is described in the prior art (see, for example, Jang et al. in U.S. Pat. No. 6,072,237). Suffice it to say that an important part of this process is that an etch-stopping layer of silicon nitride 18 is first laid over the area that is to be contacted before the hole for via 19 is formed. This extra step allows said via hole to be substantially overetched while protecting the underlying material.
While the borderless contact process and structure work as intended, later work revealed that, at least in some cases, devices contacted through borderless contacts of the type shown in FIG. 1 were undergoing some performance degradation. Further investigation has shown that, even though the silicon nitride etch stop layer 18 is removed from the floor of the via hole before the via hole is filled with metal, damage to the silicon at the edges of the via was occurring in the form of dislocations that propagate downwards into the silicon. As is well known, such dislocations have a significant impact on device performance.
The problem to be solved by the present invention was therefore how to provide high quality borderless contacts without in any way impacting device performance.
As part of a routine search of the prior art, several other examples of borderless contacts were encountered. These were U.S. Pat. No. 6,133,105 (Chen et al.), U.S. Pat. No. 6,083,824 (Tsai et al.), and U.S. Pat. No. 5,677,231 (Maniar et al.). The use of an oxide layer as an etch stop layer is mentioned by Chien et al. in U.S. Pat. No. 6,110,827.
It has been an object of the present invention to provide a borderless contact for use in a silicon integrated circuit.
Another object has been that said contact be free of dislocations in the substrate at the interface between the contacting plug""s edge and the silicon surface that it contacts.
A further object has been to provide a process for manufacturing said borderless contact.
These objects have been achieved by introducing a buffer layer between the silicon surface and the silicon nitride layer used as an etch stop layer during formation of the borderless contact. Suitable materials for the buffer layer that have been found include silicon oxide and silicon oxynitride. Experimental data confirming the effectiveness of the buffer layer are provided together with a process for its manufacture.